Digital filters

ABSTRACT

A transversal type of digital filter is disclosed which uses substantially less hardware than previously known types. Conventional multiplying devices are eliminated by use of a read only memory containing a table of squares and addressed both by weighted value samples of the input signal and by values of the input signal. The weighted values are accumulated and corrected by the use of the second squared values addressed by the value of the signal sample to generate a sample of a filtered output signal.

United States Patent Nussbaumer Oct. 21, 1975 [54] DIGITAL FILTERS3,777,130 12/1973 Croisier et al. 235/152 Inventor: Henri J NussbaumerLa Gaude 3,822,404 7/1974 Croisler et al. 235/156 X France [73]Assignee: International Business Machines 523 33; jggzf grgsisCorporation, Armonk, NY.

[22] Filed: Dec. 3, 1974 21 Appl. No.: 529,205 [57] ABSTRACT Atransversal ty e of di ital filter is disclosed which P g [30] ForeignApplication Priority Data uses substantially less hardware thanpreviously known Dec. 11, 1973 France 7345377 types- Conventionalmultiplying devices are eliminated by use of a read only memorycontaining a table of 52 vs. C] 235/156; 328/167; 333/70 T Squares andaddressed both y weighted value samples 51 Int. cm G06F 7/38 of theinput Signal and by values of the input Signal- [53] Fi ld of Search235/15 152; 333/70 T, The weighted values are accumulated and corrected333/13 2 32 /167 by the use of the second squared values addressed bythe value of the signal sample to generate a sample of 56] ReferencesCited a filtered output signal.

UNITED STATES PATENTS 3 Claims, 5 Drawing Figures 3,737,636 6/1973Esteban 235/152 T5 )Gi l2 VE Xi A ADD 21 m 22 ll II B 1 ROM H c H l l Im I1 ii E ,(12 VF [2 G3 l R2 f Tl'\p-- y] 1 H n F US. Patent Oct. 21,1975 Sheet2of3 3,914,588

02 mm 0; :1 N.X a; H 0 0; N H\ m 8; a 03 00 M w 00 0 I N e h. 0200i j jE L E FIT 2 0 0 0 0 0 0 0 0 0. 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0.0 0 0 0 00 0 0.0 22:01:00 u 00 n E u 5 w h U.So Patent Oct. 21, 1975 Sheet3of33,914,588

FIG.2B

DIGITAL FILTERS OBJECTS OF THE INVENTION This invention relates todigital filters.

A digital filter is a device used to determine the values of thesuccessive samples Y, of a filtered output signal Y by forming the sumsof algebraic products of the successive values of samples of an inputsignal X. More specifically, if x,-. is the sample at instant (i-k) ofan input signal x to be filtered, the sample Y, of the filtered signalat instant i can be derived from the expression where the a,, areconstant coefficients which are a function of the characteristics of thedesired filter. A filter capable of performing operation (1) is called atransversal filter with n coefficients. However, sample Y, can also beobtained from an expression-which uses the previously computed samplesY, This can be done by means of a so-called recursive filter whichprovides samples Y,- that satisfy an expression of the type 1 k i-k fora number n of coefficients which is the same as for the transversalfilter mentioned above.

It will be observed that, whether the filter is of the transversal or ofthe recursive type, the samples Y, of the filtered signal can beexpressed as n r k' I-A- where the 04 represent coefficients a and b,and the z,- represent data samples Y,-. and/or x Thus, in the generalcase, n multiplication operations, hence n multiplier devices, arerequired to obtain Y,-. Since multipliers are expensive devices, it ishighly desirable to reduce their number to a minimum. In the past,various filter structures have been proposed which allow the number ofmultipliers required to be reduced by up to approximately 50%. Such areduction constitutes a significant improvement and would be entirelysatisfactory in many applications. However, in those applications whichrequire the use of a considerable number of filters, said structures arestill quite expensive.

Other filter structures have been proposed, which can be made toaccomplish various functions using multiplexing techniques. The maincomponent of these prior art filters is a memory storing the partialresults of the operations summarized by expression (3) above. The valuesof the samples of signals x and y are stored in digital shift registersand serve as storage addresses to control data fetches from a memory,the re sult y, being obtained by means of simple logical operationswherein the data fetched from the memory are accumulated andshifted.Such a filter is described, for example, in French Pat. No. 70 47123filed by the same assignee on December 17, 1970 and corresponding to US.Pat. No. 3,777,130 issued on Dec. 4, 1973. and corresponding toapplicants US. Pat. application Ser. No. 513,797 filed on Oct. 10, 1974.However, the cost of these filters in the larger embodiments may wellbecome prohibitive due to the fact that the memory size required is anexponential function of the number of coefficients and that theaccumulator is relatively complex. Furthermore, whenever the transferfunction of the filter is to be changed, the entire contents of thememory must be modified. This implies the use of an auxiliary memory tostore all of the coefficients to be used for the desired transferfunctions, and of a processor to compute on a demand basis the newpartial results to be stored in the main memory.

Accordingly, the main object of the present invention is to provide adigital filter using a memory whose contents are independent of thetransfer function of the filter.

The foregoing and other objects, features and advantages of theinvention will be apparent from the following more particulardescription of a preferred embodiment of the invention, as illustratedin the accompanying drawings.

FIG. 1 is a schematic diagram illustrating a preferred embodiment of afilter realized in accordance with the present invention.

FIG. 1A shows timing curves illustrating the timing relations of thecircuitry in FIG. 1.

FIGS. 2A and 2B are schematic diagrams illustrating data storage devicesthat can be used in the filter of the present invention.

FIG. 3 is a schematic diagram of another embodiment of the filter of thepresent invention.

As previously mentioned, the expression which the samples Y,- of thefiltered signal must satisfy is essentially the same whether atransversal or a recursive fil ter is used and the basic principle ofthe present invention applies equally well to either type of filter. Forsimplicity, a transversal filter will be described hereinafter. Theequation associated with such a filter is:

Hence,

If Y, is to be derived from Eq. 4, a single addition will be required toobtain the term W which is constant for a given filter. The other twoterms U, and V,- can be obtained in a relatively simple manner by usingas basic element a memory storing the squares of the values of digitizedsamples, said memory being referred to hereafter as a squares memory.All that is required to obtain U, is to perform the operation x x a andto address the squares memory using the value of x and then to addtogether the values thus fetched from the memory. The elements whichcomprise the term V,- can also be obtained from the squares. memory bysetting a,,=0. Assuming by way of example that the inputs representingthe samples of the x form, as well as the coefficients, comprise threesignificant bits, that is, three bits defining their amplitude, then allwords x can be defined by means of four bits. Any x will be obtained byaddressing the memory using the value x x a, as shown in Table l.

of II is passed to a gate A2 and the outputs of gates A1 and A2 arecombined in an OR circuit 01. When inversion is used, the transfer pathis through inverter I1. AND gate A2, hich is activated by the complementof signal T2, i.e., T2, and OR circuit 01. The output value provided byADD 2 is sent either to a register R1 through a set of gates G1 whensignal T3 is logically one, or to a register R2 through a set of gatesG2 when T3 has a logical zero value. The outputs from R1 and R2 are sentto the input D of adder ADD 2 through a set of gates G3. Input Dreceives the output from R1 through AND gates A3 and OR circuits 02 whensignal T1 has a logical one value, and receives the output from R2through AND gates A4 and OR circuits 02 when T1 has a logical zerovalue. Additionally, the output from R2 provides the filtered signal Y,at output V while the output from R1 provides information on the energyof the filtered signal at V It should be noted that the circuits shownat I1, Al, A2, 01, G1, G2, and

TABLE 1 Address x x 2 2 2 2 2" 2 2 2 2" 2 2 2 0 0 0 0 0 0 O 0 0 O 0 0 00 0 l 0 0 0 0 O 0 0 l 0 0 l 0 O O 0 0 0 l 0 0 0 O l l 0 0 0 0 l 0 0 l 0l 0 0 0 0 0 l 0 0 O 0 0 l 0 l 0 0 O l l 0 0 l 0 l l 0 0 0 l O O l 0 0 0l l l 0 0 l l 0 0 0 l l 0 0 0 0 l 0 0 0 0 0 0 l 0 0 l 0 l 0 l 0 0 0 l l0 l 0 0 l l 0 0 l 0 O l 0 l l 0 l l l l 0 0 l l l 0 0 l 0 0 l 0 0 0 O ll 0 l l 0 l 0 l 0 0 l l l l O l l 0 0 0 l 0 0 l l l l l l l O 0 0 0 lReferring now to FIG. 1, a schematic diagram of a preferred embodimentof the invention is shown. It will be assumed hereafter that the samplesof the x form of the signal to be filtered are coded using asign/amplitude code such that the corresponding binary words solelyconsist of one bit defining the sign of the sample and of several bitsdefining its amplitude. The latter bits are received sequentially andfed into a device which compresses data in time. This device allows thesamples to recirculate in such a way that during the time intervalbetween two consecutive input samples x, and x,-.,, a number of samplesreceived earlier are available at the output of the filter, as willlater be described in detail. These operations may be performed, forexample, by the compression device described in French Patentapplication No. 73 38741 filed by the same applicant on Oct. 23, 1973and corresponding to applicants US. Pat. application Ser. No. 513,797filed on Oct. 10, 1974, which device includes a high speed shiftregister and associated logic circuits. It should, however, be notedthat, for the purposes of the present invention, all of the bits of agiven sample x are provided in parallel form and are then sent to the Ainputs of a parallel adder ADD 1, the B inputs of which receive the bitsof related coefficient a that are provided by a simultaneously operatingmemory labeled COEF. The output from ADD 1 is used to address a squaresmemory labeled SQ-ROM. The value fetched from the latter is fedto a gateA1 and to an inverter [1. The inverted output G3 are in fact reproducedon each of the conductors of the busses 21, 22, 23, and 24 along whichtravel the bits of the value fed thereto since all bits of a given valueare processed in parallel.

Before describing the operation of the embodiment shown in FIG. 1, itmay be well to point out that fewer operations than might be supposedare necessary to obtain the term V,. Since it follows that VI I-l i-iI-n-I V,- can, therefore, be obtained by updating the term V that waspreviously computed while detennining Y This requires no more than twoadditional references to memory SQ-ROM.

To explain the operation of the filter, it will be assumed by way ofexample that the filter has six coefficients, a, to a and that thevalues of the input samples x, are available in the sequence shown inFIG. 1A, at the output of the data compression device. The train of datavalues of the input samples x, may be thought of as consisting ofsequences the duration of which is equal to the sampling period T of thesignal to be filtered. During each of these sequences, the filter mustcompute a sample Y, that will satisfy the expression n E a 2, a} 1 0 11W having a constant value for a given filter.

The next sample (3), Y will have the value Y1 am, (1 x (1 x 0 x 0 x aand consequently its corrective term (W+V will be Thus, the transitionfrom Y to Y-, necessitates the updating of the corrective term, which isdone by adding the value x and subtracting the value of x Each sequenceof operations intended to form a sample of the filtered signal ends withsuch an updating of the corrective term. For example, at the end of theperiod preceding that during which Y is to be formed, i.e., end ofperiod (2), input A of adder ADD 1, FIG. 1, received x while input Breceived zero. The output from ADD 1, x x was then used to addressmemory SQ; ROM which provided x on bus 21. Since signal T2 had at thattime a logical one value (T2=0), x inverted by interter II was sent toinput C of adder ADD 2 through AND gate A2 and OR circuit 01. Becausesignal Tl also had a logical one value, the contents of register R1,namely, the corrective term (W+V were sent to input D of adder ADD 2through AND gate A3 and OR circuit 02. Adder ADD 2 then performed theoperation (W+V x and fed the result to R1 due to gate G1 being activatedby signal T3, thereby partially updating the corrective term. At thebeginning of the next period, that is, the period (3) during which Y isto be formed, x is received at input A of ADD 2 and zero at input B. Theoutput from ADD 1, x addresses memory SQ-ROM which provides x Sincesignal T2 has at this time a logical 1 value, x is sent unchanged toinput C of adder ADD 2 through A1 and 01 while input D receives thecontents of R1 through G3, as described above. The corrective term(W+V-,) is thus obtained and stored in register R1. The next term x isthen received at input A of ADD 1 while coefficient a is received atinput B. Memory SQ-ROM addressed by the value (a +x,) provides the wordcorresponding to (a,,+x,) to ADD 2 since signal T2 then has a logicalone value. Because signal T1 also has a logical 1 value, input D of ADD2 receives the contents of register R1 through G3. Adder ADD 2 thenperforms the operation (W+V (.r +a the result of which is gated toregister R2 through G2 under control of the TI; signal. Next, x and aare received at the inputs of ADD 1 and memory SQ-ROM provides (x +aThis word is fed to register R2 the contents of which then become (W+V(x +a,,) (x +a Thereafter, the above operations are repeated until R2contains:

Y is then passed on through a gate (not shown in FIG. 1) located atoutput VF.

The term x is then received at input A of adder ADD 1. The correctiveterm for Y is partially updated as described above and a new cycle isinitiated.

Most of the components of the device of the present invention are of aconventional nature and will not be described in detail. Suffice it tosay here that parallel adders ADD 1 and ADD 2 may be of the general typedescribed, for example, in the book entitled, Arithmetic Operations inDigital Computers, by R. K. Richards, and more particularly of the typeillustrated in FIG. 4-1, page 84, providing that the negative words arecomplemented, or in FIG. 4-28, page 123, of said book. The structure ofthe memories may be of any conventional type, but in order to minimizetheir cost,

. it is necessary to reduce their size as much as possible.

This may be done by using the methods of operation described hereafter.Because the size of a memory capable of storing all of the wordsrequired is a direct function of the number of bits comprised in theaddress, the elimination of a single one of these bits will result inthe memory size required being reduced by half. Since a sign/amplitudebinary code has been selected in this example and the word provided bymemory SQ-ROM is independent of the sign, the latter need not beincluded in the address. In addition, if we call X the memory addressand X(O), X(l), X(2), the various O or I bits which define itsamplitude, we may write:

X may also be written X=X(O)+X', where X'2 X( 1) 4 X (2) The lowestorder bit of X' being always zero, the effect will be the same as if Xhad a length 1 bit less than X. Also, if X(O) 0, its contribution to Xis nil and X =X however, if X(O) l, X can be obtained from theexpression X l+2.X+X' Accordingly, the memory storing the values X canbe replaced by a memory storing the values X' It will be observed that Xis always even, so that its lowest order bit is zero. This bit istherefore unnecessary in the memory address. In other words, the addressof the memory storing the values X (referred to hereafter as memory x'comprises one bit less than that of the memory storing the values X Thispermits reducing the memory size by half, but a scheme such as thatshown in FIG. 2A must then be used to obtain X In this scheme, bit X(O)controls a gate G. When X (0) O, gate G is deactivated and the addressedmemory X feeds a group of inputs, Gl, of parallel adder ADD 3 whichprovides X It should be noted that memory X does not supply the twolowest order bits (having weights 1 and 2), both of which are alwaysequal to zero. When X(O) l, gate G is activated and the second group ofinputs, G2, of ADD 3 receives the value 2X, which is obtained from X byshifting the bits one position to the next higher order. To obtain X itis further necessary to force a binary 1 into the carry input of thatstage of ADD 3 which processes the lowest order bit. Thus, the operationX X 2X l is performed.

For example, if the value X 11 (so that X 196 in decimal notation) sothat X(O) 0, gate G remains closed and the output therefrom is anall-zero value. Memory X is addressed by means of the value 111 andprovides the value 110001, to which is appended the two lowest orderbits which, as previously mentioned, are always 0. Thus, the value X11000100, or 196 in decimal notation, is obtained on bus 21.

To take another example, if X 11 l l, or 15 in decimal notation, X(O) 1,gate G is activated and the group of inputs G2 receives 11100 whilememory X which is addressed by means of the value 1 11, provides theterm 1 10001 as in the previous example. Since two low order zeros areappended thereto, as explained above, the group of inputs G1 receivesthe value 1 1000100. This is added to the term 1 l 100 from G in ADD 3,which yields 111000000. Since a binary 1 is forced into the carry inputof that stage of ADD 3 which processes the lowest order bit, there isfinally obtained X 11100000+1 11100001 or 225 in decimal notation.

Thus, regardless of whether X l110 or 1111, the same memory position ofX is addressed, thereby allowing the memory size to be reduced by half.

From the foregoing, it will be seen that the reduction in the memorysize is achieved by reducing the number of words to be stored therein.The memory size could be reduced still further by reducing the number ofbits comprising each stored value, without affecting the accuracy of theresults obtained. Since bit X(O) is used as a gate control and is notutilized as a part of the address of memory X we may write X O.X(0) 2 X1 2 x 2) 2 x0 where X comprises n+1 bits.

The latter expression shows that the bits with weights 1, 2, 4, 8 and 16in X can readily be obtained by means of simple logical operations.Accordingly, these bits need not be included in the words stored inmemory X This memory can then be implemented in ac cordance with thescheme illustrated in FIG. 2B. The bits having weights 1, 2 and 8 arealways zero and may be ignored, i.e., the inputs of group G1 whichprocess these bits receive no signals. The value of the bit with weight4 is identical with X(l) and that of the bit with weight 16 can b eobtained by performing the logical AND operation X(1).X(2). The factthat these five bits need no longer be stored in memory X results in asubstantial saving in storage space. This explains the use in thediagram of FIG. 2B of an inverter 25 which inverts bit X( l) and an ANDcircuit A. The diagram of FIG. 28 illustrates the methods of operationdiscussed above.

From the foregoing, it will be apparent that the main advantage of thepreferred embodiment of the invention is to minimize the cost of thememories required. However, this in no way limits the invention to thetype of filter described hereinabove. Should future technologicaldevelopments make it possible to reduce the cost of the memories, otherembodiments of the invention might be deemed preferable. For example, itmight be desirable to use a slightly more complex squares memory inorder to eliminate the circuit that serves to update the corrective termsince, from the expression we may also derive n n 2 2 i-47 0 2 t-Combining expressions (4) and (5), we get A schematic diagram-of adevice capable of performing the operations represented by expression 6is shown in FIG. 3. The values of the samples of x are simultaneouslysent on bus X, to one input of each of the identical parallel adders ADD1 and ADD 1. Similarly, the coefficients for those samples are sent toboth of the other inputs of these adders, those intended for ADD 1 beingfirst inverted by an inverter 11. The output term from ADD 1 is used toaddress the same memory SQ- ROM as has been described above. The outputterm from ADD 1 is used to address a second memory SQ- ROM which isidentical with SQ-ROM. Since adders ADD 1 and ADD 1 are identical, itwould be possible by the use of buffer registers to eliminate either ofthem and to cause the remaining one to alternatively perform its ownfunctions and those of the eliminated adder by using a multiplexingtechnique. Similarly, either one of identical memories SQ-ROM and SQ-ROMcould be eliminated. The two words fetched from the memories SQ-ROM andSQ'-ROM should be subtracted from each other in a subtractor stage S,with the data provided by S being accumulated n times. This accumulationwould be performed as previously, using a parallel adder (ADD 4) and aregister R3.

The input data compression circuit for the device of FIG. 3 is slightlydifferent from that previously described since the coefficients do notoccur in the same sequence as before due to the elimination of thecoefficients zero that were necessary to process the corrective term.The new sequence is simply a a a, a a a,.

for that received six sample times earlier, thus:

x x x x x x x, x x x x x, x x x x, x, etc. The compression device whichcan perform this that the capacity of the compression register and theclock rate that controls the circulation of the words within thisregister are modified to reflect the new sequence of the samples x Whilethe invention has been particularly shown and described with referenceto a particular embodiment thereof, it will be understood by thoseskilled in the art that the foregoing and other changes in form anddetail may be made therein without departing from the spirit and scopeof the invention.

What is claimed is:

1. A digital filter for generating processed output samples of a signalY from input terms representing sequential values of samples of an inputsignal X, said filter comprising:

a. means for algebraically and cyclically adding sequences of predefinedcoefficients to the sequence of terms representing the latest values ofsamples of the data to be filtered;

b. a memory storing the squares of the values of all possible sumsresulting from the operations performed by said adding means;

c. addressing means for said memory to receive one of said sums fromsaid adding means and to control readout from said memory of thecorresponding square value; and

d. means for accumulating said square values fetched from said memoryduring each of said sequences to provide a corresponding sample of afiltered output signal Y.

2. A digital filter of the type wherein a sample Y,- of

a desired filtered output signal at instant i is generated by theaccumulation of the products of the values of samples x of an inputsignal x and corresponding coefficients a said filter characterized inthat it includes:

a. a first means for generating the term U defined by the expressionsaid first means including:

i. sum means for providing an address value obtained by adding a firstcoefficient value a to the value of a sample x ii. a memory storing thevalues of the squares of all possible address values;

iii. means for addressing said memory, using said address value fromsaid sum means, and for fetching from said memory the valuecorresponding to (x a iv. an accumulator to receive said fetched value;

and

v. means for repeatedly operating said sum means and said addressing andreadout means with the value of k increased by increments of l until k=nand accumulating said values fetched from said memory;

b. a control means including a second accumulator for also addressingsaid memory to provide and accumulate the squares of the values of saidinput samples and a correction factor to generate a corrective term V; Wexpressed as c. and another summing means for adding said correctiveterm to the result of the operation performed by said first means.

3. A digital filter of the type wherein the value of a sample Y, of thedesired filtered output signal at instant i is obtained by accumulatingthe values of samples of an input signal x weighted by correspondingcoefficient values, characterized in that said filter includes:

a. a storage device to provide sequences of coefficient values;

b. a first means for forming addresses by adding the filter coefficientsto corresponding samples of the signal x to be filtered;

c. a memory having at each storage address, a value representing thesquare of the memory address;

d. a second means for addressing said memory storing the squares of theaddresses, using the address values provided by said first means;

e. a register means for accumulating the values thus fetched from saidmemory;

f. a third means for forming a second set of storage addresses bysubtracting the filter coefficients from corresponding ones of saidconsecutive samples of the signal x to be filtered;

g. a second squares memory;

h. a fourth means for addressing said second squares memory, using thevalues supplied by said third means;

i. a fifth means for subtracting the values read out from said secondsquares memory as a result of the addressing performed by said fourthmeans from the accumulation perfonned by said second means.

1. A digital filter for generating processed output samples of a signalY from input terms representing sequential values of samples of an inputsignal X, said filter comprising: a. means for algebraically andcyclically adding sequences of predefined coefficients to the sequenceof terms representing the latest values of samples of the data to befiltered; b. a memory storing the squares of the values of all possiblesums resulting from the operations performed by said adding means; c.addressing means for said memory to receive one of said sums from saidadding means and to control readout from said memory of thecorresponding square value; and d. means for accumulating said squarevalues fetched from said memory during each of said sequences to providea corresponding sample of a filtered output signal Y.
 2. A digitalfilter of the type wherein a sample Yi of a desired filtered outputsignal at instant i is generated by the accumulation of the products ofthe values of samples xi-k of an input signal x and correspondingcoefficients ak, said filter characterized in that it includes: a. afirst means for generating the term Ui defined by the expression
 3. Adigital filter of the type wherein the value of a sample Yi of thedesired filtered output signal at instant i is obtained by accumulatingthe values of samples of an input signal x weighted by correspondingcoefficient values, characterized in that said filter includes: a. astorage device to provide sequences of coefficient values; b. a firstmeans for forming addresses by adding the filter coefficients tocorresponding samples of the signal x to be filtered; c. a memory havingat each storage address, a value representing the square of the memoryaddress; d. a second means for addressing said memory storing thesquares of the addresses, using the address values provided by saidfirst means; e. a register means for accumulating the values thusfetched from said memory; f. a third means for forming a second set ofstorage addresses by subtracting the filter coefficients fromcorresponding ones of said consecutive samples of the signal x to befiltered; g. a second squares memory; h. a fourth means for addressingsaid second squares memory, using the values supplied by said thirdmeans; i. a fifth means for subtracting the values read out from saidsecond squares memory as a result of the addressing performed by saidfourth means from the accumulation performed by said second means.